Elevate Semiconductor is at the forefront of shaping the future of semiconductor technology, driving innovation to enable the next generation of testing. We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to-market and enhanced capabilities. Our diverse product portfolio includes standard, semi-custom, and custom SKUs, all engineered for longevity and compatibility across evolving technological advancements. By focusing on low-power, high-density designs, we aim to lower the cost of testing while exceeding expectations on every project.
Join us in advancing the cutting edge of semiconductor innovation!
The Position
We are seeking a highly skilled Senior Analog Layout Engineer to join our team in developing state-of-the-art integrated circuits (ICs). In this role, you will handle the physical layout and verification of highly complex, high-voltage, and mixed-signal solutions using advanced process technologies, ranging from 65nm CMOS to 100+V BCD. You will collaborate with a cross-functional team to optimize silicon design, leveraging mentorship and support from senior engineers to deliver innovative and cost-effective solutions.
Must be able to work onsite in San Diego,C CA.
Responsibilities
As the sole Layout Design Engineer in the organization, you will take full ownership of physical layout activities from block-level to full-chip integration. Your responsibilities will include:
- Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level
- Conducting floorplanning and placement of circuit components to optimize area, performance, and power
- Verifying layouts using industry-standard tools for LVS (Layout vs. Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
- Collaborating closely with design engineers to understand circuit specifications and ensure layout accuracy
- Working with cross-functional teams, including digital design and packaging, to optimize overall chip performance
- Troubleshooting and resolving issues related to layout verification and manufacturing