Website:
questglobal.com
Job details:
Job Requirements
We are looking for
motivated and enthusiastic fresh graduates to join our
ASIC / SoC Design Verification team. The candidate will work closely with senior verification engineers to develop and execute
SystemVerilog/UVM-based verification environments and Tests for
IP and SoC-level projects, supporting full verification lifecycle from
test planning to coverage closure.
Key Responsibilities
- Understand ASIC / SoC specifications and contribute to verification planning
- Develop and enhance SystemVerilog / UVM testbenches
- Write directed and constrained-random test cases
- Run simulations and debug failures using industry-standard EDA tools
- Analyze functional and code coverage, and assist in coverage closure
- Support regression runs and report issues clearly
- Work with senior engineers to debug RTL issues
- Follow verification best practices and internal DV guidelines
Work Experience
Mandatory
- Strong fundamentals in Digital Electronics & System architecture
- Strong knowledge in SystemVerilog/UVM methodology and coding
- Good Understanding of ASIC Design and Verification flow
- Familiarity with functional simulation concepts
- Good problem-solving and debugging mindset
- Exposure to AMBA Protocols ( AXI/AHB/APB)
- Internship/ Academic projects in RTL / DV
- Exposure to Linux
Good to Have
- ARM or RISC CPU Architecture knowledge
- Basic Understanding on Verification architecture and Test bench components
- Basic understanding of GLS, Low Power simulation concepts
- Exposure to Simulation tools ( VCS/Xcelium/Questa) and Debug tools (Verdi/Simvision)
Behavioral Expectations
- Good Communication skills
- Ability to work in a team environment
- Willingness to learn and adapt quickly
Click on Apply to know more.