- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Python
- cross functional
- ethernet
- Gate
- IP
- Perl
- TCL
- PCIe
About the role
Proxelera
Website:
proxelera.com
Job details:
Minimum Qualifications:
- Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- Track record of first-pass success in ASIC development cyclesAt least 5 years of relevant experience
- Hands-on experience in Verilog, SystemVerilog, UVM , C/C, Python based verification
- Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas along with functional verification - RDMA, PCIe, SRIO & Ethernet, 400G Mac, RDMA, TSO, LRO, PSP,ROCE (RDMA over converged Ethernet), Congestion Control etc
- Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
- Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup
- Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments
- Experience using analytical skills to craft novel solutions to tackle industry-level complex designs
Demonstrated experience with effective collaboration with cross functional teams Preferred
Click on Apply to know more.
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