Mulya Technologies
Website:
mulyatech.com
Job details:
Digital Design Engineer
Location: Greater Bengaluru Area (Hybrid)/ Greater Hyderabad
we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
. Job Title: Design Engineer (Junior) Location: Hyderabad/Bangalore Job Type: Full-Time Experience Level: 2 to 5 Years VLSI Domain: Front-End Logic Designer
Job Summary: We are seeking a highly motivated Fresh Graduate or Junior RTL Front-End IP Designer to join our ASIC Design team. This role is ideal for candidates passionate about digital hardware design and eager to build industry-standard Intellectual Property (IP) blocks used in cutting-edge SoCs.
You will contribute to Register Transfer Level (RTL) design, simulation, and verification of reusable and configurable IP blocks used in high-performance, low-power semiconductor products. Key Responsibilities:
Contribute to RTL design and development of digital IP blocks using Verilog/System Verilog or VHDL. Assist in micro-architecture design based on functional specifications and system requirements. Develop and maintain design documentation, interface definitions, and design reviews.
Work closely with verification engineers to support testbench development and debugging RTL bugs. Run linting, synthesis checks, CDC analysis, and functional simulations. Understand and contribute to low-power design, clock domain crossings, and timing-aware RTL development.
Assist in the integration of IP into SoC subsystems, ensuring clean handoƯs and documentation. Participate in code reviews, design reviews, and team knowledge-sharing sessions. Learn and apply industry-standard flows for synthesis, timing analysis, and version control (e.g., Git, Perforce).
Required Qualifications: Bachelor’s degree (B.E./B. Tech) or Master’s (M.E./M. Tech) in Electronics, Electrical, or Computer Engineering or related field. Solid academic background in digital logic design, computer architecture, and hardware design languages (HDL). Familiarity with Verilog/System Verilog and hardware simulation tools (ModelSim, VCS, Questa).
Understanding of FSMs, Pipelining, Datapath/control design, and digital arithmetic. Exposure to basic scripting (Python/TCL/Perl) and Linux environment. Strong problem-solving skills and willingness to learn new tools, standards, and methodologies.
Preferred Qualifications: Internship or coursework in ASIC/FPGA design or RTL verification. Basic knowledge of AMBA bus protocols (AXI, AHB, APB). Exposure to low power techniques (UPF) or timing concepts (setup/hold, STA).
Familiarity with Git, JIRA, or any version control and task management systems.
Soft Skills: Eagerness to learn and grow in the semiconductor industry. Attention to detail and structured thinking. Good communication skills and ability to work in a team. Proactive attitude towards challenges and deadlines. What We OƯer: Mentorship and training from experienced RTL and SoC engineers. Exposure to full-chip design flows and state-of-the-art IPs. Opportunity to work on industry-leading technologies (AI & HPC). Clear career growth path into RTL architect, IP lead, or verification/design specialization.
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Click on Apply to know more.