SmartSoC Solutions Pvt Ltd
Website:
smartsocs.com
Job details:
Large Design Servicess Organization with more than 1000 employees
TITLE: DFT Lead Engineer
LOCATION: GREATER BENGALURU AREA
DFT Lead
Experience - 8+yrs
Location - Bangalore
Compensation Range - 5.5x to 6x
RTL DFT insertions & verification
SSN implementation and validation
IJTAG (IEEE 1687) insertion & verification – Block and SoC level
MBIST insertion, memory repair configuration & verification – Block and SoC level
EDT-based scan compression insertion and validation
Netlist insertions & Pattern verification
Gate-level scan stitching and DRC checks
LBIST architecture implementation and validation
ATPG pattern generation (stuck-at/transition) and GLS simulations
Coverage analysis, debug, and pattern optimization
Post-silicon bring-up, ATE support, and silicon debug
Uday
muday_bhaskar@yahoo.com
www.mulyatech.com
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