Ultrabot Innovations
Website:
ubis.in
Job details:
We are looking for a DFT Engineer with strong ATPG expertise to work on advanced SoC designs. The ideal candidate should have hands-on experience in test pattern generation, coverage improvement, and silicon bring-up support, along with exposure to at least one of the key supporting domains like Pattern Generation, Gate-Level Simulation, or DFT Linting.
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Key Responsibilities
* Develop and implement DFT architecture for complex SoCs
* Perform ATPG pattern generation, validation, and debug
* Drive stuck-at, transition, and path delay fault coverage closure
* Analyze and improve test coverage and pattern efficiency
* Work on scan insertion, compression techniques, and MBIST/LBIST (if applicable)
* Collaborate with design and verification teams for DFT sign-off
* Support post-silicon validation and failure analysis
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Mandatory Skills
* Strong experience in ATPG (Automatic Test Pattern Generation)
* Hands-on with tools like Mentor Tessent / Synopsys TetraMAX / Cadence Modus
* Solid understanding of:
* Scan architecture
* Fault models (SAF, Transition, etc.)
* DFT methodologies for ASIC/SoC
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