SEMI LEAF
Website:
semi-leaf.com
Job details:
DFT Engineers - [Scan / ATPG / MBIST / SSN]
Job Summary :
We are looking for a skilled DFT Engineer with hands-on experience in scan insertion, ATPG, MBIST, and SSN (Scan Shift Network). The candidate will be responsible for implementing and validating DFT architectures to ensure high test coverage and product quality for complex SoC/ASIC designs.
Key Responsibilities :
- Implement and validate scan architecture (full scan, compression, chain stitching, scan reordering)
- Design and integrate SSN (Scan Shift Network) for efficient test data distribution
- Perform ATPG (Automatic Test Pattern Generation) for stuck-at, transition, and path delay faults
- Analyze and improve fault coverage, debug coverage issues, and optimize pattern count
- Implement and verify MBIST (Memory Built-In Self-Test) for embedded memories
- Work on BIST architectures including LBIST/MBIST integration and validation
- Perform DFT DRC checks, test rule analysis, and fix violations
Required Skills :
- Scan insertion & compression techniques
- SSN / Scan network architecture
- ATPG (stuck-at, transition, bridging faults)
- MBIST implementation & debugging
- Knowledge of JTAG / IEEE 1149.1 / boundary scan
- Understanding of low power DFT (power-aware ATPG, clock gating, UPF)
Tools and Technologies :
- Hands-on experience with industry tools such as:
- Synopsys DFT Compiler / TetraMAX / TestMAX
- Cadence Modus / Encounter Test
- Mentor Tessent (Scan, MBIST, ATPG)
- Experience in Verilog/SystemVerilog
- Familiarity with Perl/Python/Tcl scripting
Preferred Qualification :
- Experience with SoC-level DFT integration
- Knowledge of compression techniques (EDT, Xpress, etc.)
- Exposure to yield analysis and silicon debug
- Understanding of physical design impact on DFT (timing, congestion)
Share you updated CV to vagdevi@semi-leaf.com
Click on Apply to know more.