Eximietas Design
Website:
eximietas.design
Job details:
Job Description:
We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles that will challenge and grow your skills in advanced silicon testing.
You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, subsystem, and SOC designs.
Core
Responsibilities:
- End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.
- Scan architecture definition and implementation at RTL and gate level, including EDT and OCC.
- Execution of block-level ATPG, DRC analysis, and coverage optimization.
- Handling of pattern simulations, including both timing and non-timing simulations.
- SOC-level integration, including pattern retargeting to subsystem and full-chip levels.
- Integration, simulation, and debug of MBIST, IJTAG, and Boundary Scan (JTAG).
- Independent debugging of DFT simulations and netlist-related issues.
- Close collaboration with design, verification, and physical design teams to ensure DFT readiness.
- Ownership of DFT sign-off activities and deliverables.
Key Responsibilities:
- Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.
- Perform scan insertion, ATPG generation, and pattern validation at block and top levels.
- Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.
- Define and execute DFT strategies aligned with project requirements and schedules.
- Support pre-silicon and post-silicon test requirements.
- Serve as the DFT point of contact for assigned projects, responsible for verification and test readiness sign-off.
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