Tsavorite Scalable Intelligence
Website:
tsavoritesi.com
Job details:
TITLE: Design Verification Engineer (Principal/SMTS)
LOCATION: GREATER BENGALURU AREA
COMPANY DESCRIPTION:
At Tsavorite Scalable Intelligence, we are pioneering the semiconductor industry’s first Omni Processing Unit (OPU)—a breakthrough composable architecture designed to power the next generation of real-time, multi-modal Agentic AI.
Founded in 2023 by a veteran team from Intel, Nvidia, Qualcomm, and Apple, we are on a mission to eliminate the cost, power, and complexity bottlenecks of legacy GPU systems. Our technology delivers a 10x performance gain at 10% of energy consumption, scaling seamlessly from edge devices to exascale data centers.
Why Engineers Join Us:
- Architectural Innovation: Work on the MultiPlexus™ fabric, a revolutionary interconnect offering petabyte-scale bandwidth and ultra-low latency.
- Full-Stack Impact: We are building everything from modular chiplets on Samsung’s SF4X platform to our Tsavorite AI Orchestration Stack (TAOS), which provides zero-switching-cost compatibility for CUDA-optimized workflows.
- Market Momentum: We emerged from stealth with over $100 million in pre-orders from Global 500 companies and sovereign cloud providers.
Key Links to Include
- Official Website: tsavoritesi.com
- LinkedIn Page: Tsavorite Scalable Intelligence | LinkedIn
- Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)
- https://www.businesswire.com/news/home/20251110678526/en/Tsavorite-Scalable-Intelligence
JOB DESCRIPTION:
You will be working on server class ARM CPUSS sub-system verification at block and SoC level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level.
OR
You will be working on High performance Ethernet at sub-system and SoC level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level
OR
You will be working on end-to-end data-path verification for high-performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels.
OR
You will be working on high performance UCIe controllers at block and SoC level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level
OR
You will be working on Memory and Networking Encryption at sub-system and SoC level for high performance high throughput flows. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level
Required qualifications
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering/Science with 11-14(SMTS) or 14+(Principal) years of relevant experience
- Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 5 yrs+ hands-on experience in IP/sub-system and/or SoC level verification
- Experience in development of UVM based verification environments from scratch.
Contact
Sumit S. B.
sumit@mulyatech.com
www.mulyatech.com
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