Design Verification Engineer
Neurealm
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Python
- end-to-end
- IP
- TCL
- FPGA
About the role
Website:
neurealm.com
Job details:
- Key Responsibilities
- - IP Integration: Develop wrappers for IPs to build integrated SoC systems on FPGA.
- - Porting & Adaptation: Port wrappers and logic across different configurations and hardware platforms.
- - Bitstream Generation: Manage the end-to-end flow from synthesis to bitfile generation and flashing onto HW.
- - System Testing: Conduct functional testing of the FPGA bitfile and overall hardware system.
- - HW Debugging: Perform deep-dive debug using on-chip logic analyzers (ILA/SignalTap) and JTAG.
- - Implementation of Fixes: Analyze hardware bugs and implement RTL or implementation-level fixes.
- Mandatory Tech Skills
- - HDLs: Strong proficiency in Verilog or SystemVerilog.
- - FPGA Tools: Hands-on experience with Vivado, Quartus, or equivalent toolchains.
- - Protocols: Deep understanding of AXI, AHB, or similar SoC interconnects.
- - Hardware Debug: Proficiency with ILA/ChipScope and external debug equipment (Logic Analyzers).
- - Build Flows: Experience with timing closure and FPGA resource optimization.
- Preferred Skills
- - Scripting: Automation experience using Tcl, Python, or Shell.
- - Emulation Platforms: Experience with Palladium, Zebu, or HAPS hardware.
- - Processor Design: Understanding of pipeline stages, memory coherency, and interrupt handling.\
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