Interex semiconductor
Website:
interexsemi.com
Job details:
About the Role
We are hiring Design Verification Engineers with strong hands-on experience in IP, Sub-System, and/or SoC verification. The ideal candidate should be proficient in SystemVerilog and UVM, capable of independently owning verification activities from planning through coverage closure.
Required Qualifications
- M.Tech (Mandatory)
- 3+ years of Design Verification experience
- Strong expertise in SystemVerilog and UVM
- Experience in IP, Sub-System, or SoC Verification
- Experience with AMBA protocols (AXI/AHB/APB)
- Strong debugging and coverage closure skills
Preferred Qualifications
- SVA experience
- Low-power verification exposure
- Python/Shell scripting
- Experience with VCS, Xcelium, or Questa
Apply
Interested candidates can send their resume to:
nagu.m@interexsemi.com
Click on Apply to know more.