Interex semiconductor
Website:
interexsemi.com
Job details:
About the Role
Interex Semiconductor is seeking experienced Design Verification Engineers to join our growing team in Bengaluru.
We are looking for engineers with strong hands-on experience in IP, ASIC, and SoC verification who can independently own verification activities from planning through coverage closure and sign-off. The ideal candidate should possess solid verification fundamentals, strong debugging skills, and experience working on complex silicon projects.
Key Responsibilities
- Develop and maintain SystemVerilog/UVM-based verification environments.
- Create verification plans, testcases, assertions, and coverage models.
- Perform IP, Subsystem, and SoC-level functional verification.
- Debug simulation failures and drive root-cause analysis.
- Execute regressions and drive coverage closure.
- Collaborate with RTL, architecture, and design teams to ensure design quality and verification sign-off.
Required Skills
- Strong expertise in SystemVerilog and UVM.
- Hands-on experience in IP/ASIC/SoC Verification.
- Verification Environment Development.
- Assertions (SVA), Functional Coverage, and Coverage Closure.
- Regression Debugging and Root Cause Analysis.
- Verification Planning and Execution.
Preferred Protocol Experience
AXI, AHB, APB, I2C, SPI, UART, PCIe, DDR, Ethernet, or USB.
Preferred Candidate Profile
- Strong understanding of verification methodologies.
- Experience working on complex real-world verification projects.
- Ability to independently drive verification tasks.
- Excellent debugging and problem-solving skills.
- Immediate joiners are preferred.
Apply
Interested candidates can apply through LinkedIn or share their updated resume to:
📧 nagu.m@interexsemi.com
If you know someone who would be a strong fit for this role, referrals are highly appreciated. Please feel free to share this opportunity within your professional network.
Click on Apply to know more.