Website:
bestnanotech.in
Job details:
Design for Test (DFT) Engineer RTL & Test Chip Architecture
Location: Bengaluru, India
Work Mode: Onsite
Experience: 5 12 Years
Industry: Semiconductor / VLSI / ASIC Design
Role Overview
We are looking for an experienced Design for Test (DFT) Engineer with expertise in RTL-based DFT implementation, Test Chip Architecture, Scan Design, ATPG, MBIST, and silicon validation for advanced ASIC and SoC designs. The role involves developing scalable DFT architectures, implementing test features at RTL, improving manufacturing test coverage, supporting silicon bring-up, and collaborating with design, verification, physical design, and product engineering teams to ensure high-quality silicon for volume production.
This opportunity is ideal for engineers passionate about building robust test solutions for complex semiconductor devices across advanced technology nodes.
Key Responsibilities
- Design and implement DFT architecture for complex SoC and ASIC designs from RTL through silicon validation.
- Develop and integrate scan chains, scan compression, MBIST, LBIST, boundary scan (JTAG), and IEEE 1500/1687 test architectures.
- Define DFT requirements during architecture and microarchitecture planning.
- Perform DFT insertion, verification, and signoff using industry-standard EDA tools.
- Generate and optimize ATPG patterns to achieve high fault coverage while minimizing test time and tester memory.
- Support RTL design teams in implementing test-friendly architectures and resolving DFT-related issues.
- Collaborate with Physical Design teams on scan reordering, clocking strategies, timing closure, and DFT-aware floorplanning.
- Work closely with Product Engineering and ATE teams during silicon bring-up, characterization, production test, and yield improvement.
- Debug scan failures, test escapes, silicon issues, and manufacturing defects using root cause analysis.
- Develop DFT methodologies, reusable IP, automation scripts, and design guidelines for future programs.
- Review test coverage reports, fault models, and quality metrics to ensure manufacturing readiness.
- Support multiple tape-outs across advanced semiconductor process technologies.
Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
- 5 12 years of hands-on experience in DFT implementation for ASIC or SoC designs.
- Strong understanding of semiconductor design flow from RTL to silicon.
- Experience supporting production test and silicon debug activities.
Technical Skills DFT Architecture
- RTL DFT Implementation
- Scan Architecture
- Scan Compression
- Test Chip Architecture
- MBIST
- LBIST
- Boundary Scan (JTAG)
- IEEE 1149.1
- IEEE 1500
- IEEE 1687 (IJTAG)
Test Generation
- ATPG
- Fault Coverage Analysis
- Stuck-at Fault
- Transition Fault
- Cell-Aware Test
- Diagnosis
- Pattern Validation
- Test Time Optimization
Design Flow
- RTL Design
- Verilog
- SystemVerilog
- Synthesis
- LEC
- CDC
- RDC
- STA
- GLS
- Low Power Design
EDA Tools
- Synopsys DFT Compiler
- Tessent
- TestMAX
- Modus
- SpyGlass DFT
- PrimeTime
- Design Compiler
- ICC2 (preferred)
Programming & Automation
- Tcl
- Perl
- Python
- Shell Scripting
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