Website:
qailashlabs.com
Job details:
Role Level: Core Engineering (Custom Analog Layout Engineer / Senior Layout Specialist)
• Location: Vijayawada (AP) / Hybrid (Open to relocation or flexible hybrid for experienced analog layout specialists)
• Experience: 3 to 6 years of direct, hands-on experience in Full-Custom AMS IC Silicon Layout with proven commercial tape-out closure
CRITICAL APPLICANT SCREENING NOTICE (PLEASE READ CAREFULLY):
• Strictly Full-Custom Analog IC Silicon Layout: This position is 100% dedicated to manual, transistor-level custom analog IC silicon layout in Cadence Virtuoso Layout-XL. It requires deep expertise in silicon design rules, analog matching, noise shielding, and parasitic extraction.
• Automated Digital Place & Route (APR / P&R) Applicants: Candidates whose background is primarily in automated digital physical design (Synopsys ICC2, Cadence Innovus, digital standard cell P&R flows) are NOT suitable for this role. Please do not apply.
• Batch Digital Physical Verification (PV) Batch Runners: Candidates whose experience is limited to executing automated DRC/LVS runscripts or fixing antenna/density violations on large digital SoCs without hands-on analog polygon layout and device matching will NOT be shortlisted.
• PCB / Board-Level Hardware Designers: Candidates with Printed Circuit Board layout (Altium, Allegro PCB, Gerber generation, SMT assembly) experience are INELIGIBLE. This is an advanced integrated circuit (monolithic silicon microchip) physical layout position.
Role Overview:
Own the transistor-level custom physical layout, critical analog matching, floorplanning, parasitic extraction (PEX), and DRC/LVS physical verification sign-off for sovereign Cryogenic Infrared Readout ICs (Cryo-ROICs) and precision mixed-signal ASICs on advanced deep-submicron CMOS and modern SOI process nodes. Working in tight collaboration with our Analog Circuit Designers, you will translate sensitive, micro-pitch analog schematics into tape-out-ready, DRC/LVS clean silicon layouts with zero external design partner dependency.
Key Responsibilities:
• Full-Custom Analog IC Layout: Execute manual polygon-level drawing and schematic-driven layout (SDL) in Cadence Virtuoso Layout-XL / GXL, adhering strictly to foundry Design Rule Manuals (DRMs).
• Extreme Aspect Ratio & Column Pitch-Matching: Floorplan and route high-density pixel unit cell arrays and 14-bit column-parallel SAR ADC banks under extreme column-pitch constraints (10 μm to 12 μm pitch).
• Precision Device Matching & Symmetry: Implement interdigitated differential pairs, common-centroid (cross-quad) topologies, dummy transistor placement, and well/diffusion proximity effect (WPE/LOD) mitigation for ultra-low offset and thermal gradient immunity.
• Capacitive DAC (CDAC) Array Layout: Floorplan and route precision Metal-Oxide-Metal (MOM) / MIM capacitor banks with shielding layers and parasitic capacitance minimization for SAR ADC linearity (high ENOB, low DNL/INL).
• Critical Net Shielding & Noise Isolation: Implement coaxial/coplanar active metal shielding for high-impedance charge-sensitive nodes (CTIA/charge amplifier inputs), protecting analog nets from digital switching noise. Implement deep N-well (DNW), triple-well isolation, and robust guard ring boundaries.
• Substrate & Body-Bias Routing: Route dedicated body-biasing grids and low-IR-drop Power Distribution Networks (PDN) while ensuring electromigration (EM) compliance.
• Physical Verification Sign-Off: Execute golden DRC, LVS, ERC, Antenna, and DFM sign-off using Siemens Calibre (Interactive / Calibre RVE), achieving 100% clean rule deck closure across multi-corner runs.
• Parasitic Extraction (PEX): Run full-chip and block-level parasitic extraction (Calibre xACT / xRC / Quantus), generating clean DSPF/SPEF/RLC extracted netlists for post-layout SPICE re-simulation and back-annotation.
• Foundry PDK Setup & Customization: Assist in Cadence Virtuoso foundry PDK bring-up (cds.lib, display.drf, techfiles, layer maps) and leverage SKILL / Python / TCL scripting or PCells to automate repetitive array and routing tasks.
• Bump Pad Array & I/O Layout: Floorplan and layout peripheral wire-bond pad rings, ESD protection clamps, and high-density micro-bump pad arrays for flip-chip hybrid focal plane array (FPA) integration.
Qualifications & Technical Skills:
• Education: B.Tech / M.Tech in Electronics & Communication, Microelectronics, VLSI Design, or Electrical Engineering.
• Experience: 3 to 6 years of dedicated, hands-on experience in full-custom Analog & Mixed-Signal IC silicon layout with at least 1–2 successfully taped-out commercial chips.
• Primary EDA Tools: Mastery of Cadence Virtuoso Layout-XL / GXL and deep proficiency in Siemens Calibre (Calibre DRC, Calibre LVS, Calibre PEX, Calibre RVE). Familiarity with Cadence Quantus / Pegasus or Synopsys ICV is a plus.
• Analog Layout Mastery: Demonstrated expertise in precision analog layout techniques: common-centroid matching, interdigitation, dummy structures, guard rings, substrate noise isolation, and WPE/LOD stress effect mitigation.
• Target Circuit Experience: Direct layout experience in precision analog blocks: SAR ADCs, DACs, Bandgap References, LDOs, Op-Amps / CTIAs, Comparators, and High-Speed Clock/Phase generators.
• Advanced Nodes (Preferred): Familiarity with advanced node design rules.
• Scripting: Working knowledge of Cadence SKILL, Python, or TCL scripting for layout automation and array generation.
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