Tech Mahindra
Website:
techmahindra.com
Job details:
Brief About Tech Mahindra – Silicon Engineering
Tech Mahindra Silicon Engineering is a key part of Tech Mahindra's semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, and industrial clients. The practice focuses on VLSI, embedded systems, and platform engineering, supporting customers from architecture and design through verification, validation, and sustenance engineering.
T
he Silicon Engineering unit works across IP, Subsystem, and SoC-level development, offering capabilities in areas such as Design Verification, RTL Design, DFT, Physical Design, Post-Silicon Validation, Embedded Software, and System Modeling & Simulation. Teams leverage industry-standard methodologies, tools, and verification frameworks to deliver high-quality, production-ready silicon solutions.B
a
cked by Tech Mahindra's global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology clients worldwide, operating as an extended engineering arm to accelerate innovation, reduce time-to-market, and ensure reliable, scalable silicon platforms. It is part of Tech Mahindra's broader engineering-led growth strategy serving multiple global industries.Ab
o
ut the RoleWe
are seeking a talented and motivated CPU Physical Design Engineer to join our Silicon Engineering team. In this role, you will be responsible for the physical implementation of high-performance CPU cores and subsystems, driving designs from netlist to GDSII while meeting aggressive power, performance, and area (PPA) targets.You
will work closely with RTL, Design, DFT, Timing, Architecture, and CAD teams to deliver world-class CPU designs for next-generation semiconductor products. This role offers the opportunity to work on advanced technology nodes and cutting-edge CPU architectures for global semiconductor leaders.Key
ResponsibilitiesDriv
- e end-to-end CPU Physical Design implementation from synthesis through signoff.Perf
- orm floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.Exec
- ute timing closure activities and optimize designs for Power, Performance, and Area (PPA) targets.Anal
- yze and resolve setup, hold, signal integrity, and congestion issues.Perf
- orm design optimization using ECO methodologies and timing-driven implementation techniques.Coll
- aborate closely with RTL, DFT, STA, and architecture teams for design convergence.Work
- on advanced technology nodes (5nm/3nm and below) and high-frequency CPU designs.Perf
- orm physical signoff checks including DRC, LVS, ERC, IR Drop, EM, and Noise Analysis.Deve
- lop and maintain implementation flows, methodologies, and automation scripts.Debu
- g design implementation issues and drive closure with cross-functional teams.Part
- icipate in design reviews, technical discussions, and customer interactions.Supp
- ort tapeout activities and ensure successful silicon delivery.Qual
i
ficationBE/BT
ech/ME/MTech degree in Electronics, Electrical, VLSI, Microelectronics, Computer Engineering, or related disciplines.Requi
r
ed SkillsStrong
- experience in CPU Physical Design / Block-Level / Full-Chip Physical DesignHands-
- on expertise in:Floorp
- lanningPower
- PlanningPlacem
- ent & OptimizationClock
- Tree Synthesis (CTS)Routin
- gPhysic
- al VerificationGood u
- nderstanding of Static Timing Analysis (STA) concepts.Experi
- ence in timing closure for high-performance designs.Knowle
- dge of signal integrity, crosstalk, IR Drop, and electromigration analysis.Hands-
- on experience with industry-standard EDA tools such as:Cadenc
- e InnovusSynops
- ys ICC2PrimeT
- imeTempus
- Experi
- ence with advanced technology nodes (16nm, 7nm, 5nm, 3nm, etc.).Strong
- scripting skills in Tcl, Perl, Python, or Shell.Good u
- nderstanding of low-power implementation methodologies.Excell
- ent debugging, analytical, and problem-solving skills.Prefer
r
ed SkillsExperie
- nce with ARM CPU, x86 CPU, RISC-V CPU, or High-Performance Compute (HPC) designs.Exposur
- e to hierarchical and full-chip implementation flows.Experie
- nce in physical signoff and tapeout activities.Knowled
- ge of UPF/CPF-based low-power design implementation.Familia
- rity with automation and flow development.Experie
- nce in advanced-node design methodologies and process technologies.Experie
n
ce Range: 5-10 YearsWhy Join
Tech Mahindra Silicon Engineering?Join a te
am of semiconductor experts delivering next-generation CPU and SoC solutions for leading global technology companies. Work on advanced-node silicon, high-performance computing architectures, and innovative semiconductor products while contributing to cutting-edge CPU Physical Design and implementation excellence.
Click on Apply to know more.
