Report

Sr Principal RTL Design Engineer

Min Experience

12 years

Location

Bengaluru, Karnataka, India

JobType

full-time

About the job

Info This job is sourced from a job board

About the role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

12+ years of experience in ASIC design
Proficient in Verilog coding, RTL design and complex control path and data path designs
Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
Experience in writing Verilog testbench and running simulations.

We’re doing work that matters. Help us solve what others can’t.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

verilog

rtl design

interface protocols

rtl checks

synthesis flow

lec

timing constraints

verilog testbench

simulations