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Lead Design Engineer - Verification

Salary

₹30 - 50 LPA

Min Experience

1 years

Location

Nanjing, Jiangsu, China

JobType

full-time

About the job

Info This job is sourced from a job board

About the role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineer – Verification

Location: Nanjing

Position Description

Specific duties include:

  • Responsible for verification plan define based on IP design SPEC.
  • Verification Test-Bench maintain and development, Circuit issue debug.
  • Understanding on ASIC verification flow, responsible for milestone delivery check

Position Requirements

  • Master degree with 1+ years or bachelor with 2+ years as an experienced digital IC verification.
  • Experienced in successful tape-out of ASIC chips
  • Familiar to UVM test-bench architecture and experienced on test-bench development.
  • Self-motivation with communication skills (spoken and written English and Mandarin)
  • Experienced in coding of SV, Perl/Python, Makefile

We’re doing work that matters. Help us solve what others can’t.

About the company

Cadence

Skills

sv
perl
python
makefile
uvm
asic