About the role
Drive key customer engagements in cooperation with local/international Field Applications team Interface with R&D team to drive and influence product development to fulfill customer requirements. Candidate should have a good knowledge of RTL design verification, gate level simulation timing & System Verilog. Knowledge about static timing analysis tool, SDC constraints is a plus. This position requires an engineer passionate about learning and diagnosing verification problems systematically to improve throughput to verify and debug cutting-edge SOCs, System ICs, and complex Ips.
About the company
Cadence Design Systems, Inc., headquartered in San Jose, California, is an American multinational computational software company, founded in 1988 by the merger of SDA Systems and ECAD, Inc.
