Design Verification Architect
Cadence Design Systems
- Experience
- 15+ yrs
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- SystemVerilog
- SVA
- Cadence Jasper
About the role
BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field; 15+ years verification experience with at least 5 years hands-on formal verification; deep expertise in property-based formal verification of complex RTL; knowledge of PCIe and UALink protocols; SystemVerilog and SVA; experience with Cadence Jasper or equivalent.
About Cadence Design Systems
Computational software provider for electronic design and system development.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.
_1548133325694.png){kind=logo}
