Website:
rtlynx.com
Job details:
🚨 HIRING | Automotive SerDes Design Verification Engineer 🚨
📍 Location: Bangalore
🏢 Company: RTLYNX Semicon India Pvt. Ltd.
⏳ Experience: 6+ Years
We are looking for an experienced Design Verification Engineer with strong expertise in SystemVerilog, UVM, Automotive SerDes and ASA IP verification.
🔹 Key Responsibilities
• Block & chip-level functional verification of ASA IP integration, ASA link data path & ASEP application streams
• Develop UVM testbench architecture for ASA IP, ASEP application layer & end-to-end CSI-2-to-ASA scenarios
• Create constrained-random tests covering PHY power-up, TDD mode switching, light sleep, speed-grade changes, IBG timing & header detection
• Integrate ASA simulation models including gate-level/behavioral models
• Perform PHY AMS / mixed-signal co-simulation
• Develop protocol checkers for ASA-ML DLL, ASEP framing, OAM transactions & LLS security frames
• Manage regressions and drive functional & code coverage closure
• Perform CDC/Reset verification using Cadence JasperGold
• Verify security scenarios including key exchange, AES-GCM tag verification, authentication & encryption modes
🔹 Mandatory Skills
✅ SystemVerilog
✅ UVM
✅ Cadence Xcelium / vManager
✅ Automotive SerDes Design Verification – Mandatory
✅ Experience in block/chip-level DV
✅ Strong understanding of verification methodology, coverage & regression
💡 Experience with ASA / Automotive SerDes / CSI-2 / ASEP protocols will be highly relevant.
📩 Interested candidates: Please share your updated CV at Shubhangini.Patil@rtlynx.com
🔁 Please share this post with relevant candidates in your network.
#Hiring #SemiconductorJobs #VLSIJobs #DesignVerification #DVEngineer #SystemVerilog #UVM #AutomotiveSerDes #SerDes #ASA #CSI2 #ASEP #CadenceXcelium #JasperGold #BangaloreJobs #ImmediateJoiner #NoticePeriod #RTLYNX
Click on Apply to know more.