Tech Lead Engineer, Design Verification
Astera Labs
- Salary
- $175k - $195k
- Experience
- 5+ yrs
- Location
- San Jose, California, United States
- Job type
- Full-time
Required skills
- SystemVerilog
- UVM
- Python
- PowerShell
- Tcl
About the role
Bachelor's degree in Electrical/Computer Engineering or related field; 5-8 years design verification experience; SystemVerilog and UVM; verification planning, testbenches, assertions, coverage; simulation and debug tools; strong leadership and communication.
About Astera Labs
Provider of connectivity solutions for AI data centers.
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