Tech Lead, Digital Design Engineer
Astera Labs
- Experience
- 3+ yrs
- Location
- San Jose, California, United States
- Job type
- Full-time
Required skills
- Synopsys
- Cadence
- UVM
- Python
- RTL
- GLS
- DFT
About the role
Bachelor's in EE required, Master's preferred; 3+ years developing complex SoC/silicon for networking or storage; expertise in high-speed protocols (PCIe, Ethernet); front-end design skills; authorized to work in the US.
About Astera Labs
Provider of connectivity solutions for AI data centers.
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