Senior Digital Design Engineer
Astera Labs
- Location
- San Jose, California, United States
- Job type
- Full-time
Required skills
- RTL
- Synopsys
- Cadence
- UVM
- Python
About the role
Bachelor's degree in electrical engineering required, Master's preferred; experience with RTL, synthesis, IP integration, high-speed protocols (PCIe, Ethernet), Synopsys/Cadence tools, DFT, UVM verification, silicon bring-up; authorized to work in the US.
About Astera Labs
Provider of connectivity solutions for AI data centers.
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