UST
Website:
ust.com
Job details:
Role Description
Job Description: Title: Assistant Engineer Role and Responsibilities 4 to 5 Years of experience with good knowledge of Design Verification(DV) background. Ability to implement sv//uvm test bench environment, generate stimulus, execute tests and debug through wave debug tools. Experience and good knowledge on AMBA is must. Experience on any of Mipi DSI/CSI/HDMI/USB would add more value
Skills
vlsi design,design verification,sv/uvm,test bench,
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