UST
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ust.com
Job details:
Role Description
Job Description:
- Deep understating and experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO)
- Knowledge of timing corners/modes, process variations and signal integrity related issues are required
- Experience in timing closure of high frequency blocks & subsystems (Ghz range )
- Experience in working full-chip STA closure, defining mode requirements and corners for timing closure.
- Strong Understanding of DFT modes requirements for timing signoff
- Good understanding of physical design flow and ECO implementation.
- Strong understanding of SDC constraints, OCV,AOCV,POCV analysis.
- Strong TCL/scripting knowledge is mandatory.
Release Comments: STA - Physical design - Power/EM/IR engineer - Physical verification - DFT engineer Deep understating and experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO)Knowledge of timing corners/modes, process variations and signal integrity related issues are requiredExperience in timing closure of high frequency blocks & subsystems (Ghz range )Experience in working full-chip STA closure, defining mode requirements and corners for timing closure.Strong Understanding of DFT modes requirements for timing signoffGood understanding of physical design flow and ECO implementation.Strong understanding of SDC constraints, OCV,AOCV,POCV analysis.5+ years experience is required. Strong TCL/scripting knowledge is mandatory.
Skills
vlsi design,sta,tempus,primetime,tweaker,dmsa,
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