UST
Website:
ust.com
Job details:
Role Description
FPGA RTL Design Engineer
- Strong Verilog/SystemVerilog design expertise
- Experience building PCIe DMA datapaths, packet generators/checkers, and memory mapped subsystems
- Familiarity with Avalon ST/Avalon MM/AXI protocols
- Implementing register maps, control logic, FIFOs, error injection blocks
- Writing synthesizable, lint clean RTL and module-level testbenches
Skills
vlsi design,verilog,pcie,fifos,rtl design,
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