UST
Website:
ust.com
Job details:
Role Description
Role Proficiency:
Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision
Outcomes
- Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.
- Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time
- On time quality delivery approved by the project lead/manager
Measures Of Outcomes
- Quality –verified using relevant metrics by Lead/Manager
- Timely delivery - verified using relevant metrics by Lead/Manager
- Reduction in cycle time and cost using innovative approaches
- Number of trainings attended
- Number of new projects handled
Outputs Expected
Quality of the deliverables:
- Ensure clean delivery of the design and module in-terms of ease in integration at the top level
- Meet functional spec / design guidelines 100% of the time without any deviation or limitation
- Documentation of the tasks and work performed
Timely Delivery
- Meeting project timelines as requested by the program manager
- Support the team lead in intermediate tasks delivery
Team Work
- Participation in team work; supporting team members/lead at the time of need
- Able to perform additional tasks in-case any team member(s) is not available
Innovation & Creativity
- Automate repeated tasks to save design cycle time as a necessary approach
- Participation in technical discussion training forum
Skill Examples
- Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)
- EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)
- Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
- Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
- Strong communication skills
- Good analytical reasoning and problem-solving skills with attention to details
- Able to deliver the tasks on-time per quality guidelines and GANTT in every instance.
- Required technical skills and prior design knowledge to execute the assigned tasks
- Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project
Knowledge Examples
- Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing
- Understanding of the technical specs and assigned tasks:
- Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill
Additional Comments
- Understand system requirements, generating system and RTL design document.
- RTL Development and develop test bench to support the verification and validation of sub system and RTL modules.
- Deliver test specifications document and test objectives.
- Align the development and validation process with cross-functional teams.
- Create internal and external specifications & user documents.
- Learn constantly, dive into new areas with unfamiliar technologies, and embrace the ambiguity of problem-solving.
- Apply critical thinking to the results/data of competitive analysis for product development.
- Work with cross-functional teams, including ASIC, Firmware, and Validation, to ensure seamless product development. Qualifications: REQUIRED:
- Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development
- Experience with AMD Vivado & Vitis SDK & VItis AI tools.
- Experience with C/C++ in developing Embedded FW & scripting automation using Python
- Experience with Petalinux build flow , familiarity with Uboot, linux driver changes and FPGA SoC debugging.
- Proven ability to work as part of a global team in multiple geographies
- B.Tech. in Electronics , Electrical , Computer Science Engineering
- Requires 8-10 years of experience in FPGA/RTL & TestBench/ embedded systems architecture
- Multi-disciplinary experience, including Firmware, HW, and ASIC/FPGA design PREFERRED:
- Knowledge of FPGA Chip to Chip interfacing & AMD FPGAs is an advantage
- Knowledge of PCIe Gen4/5/6 technology is an advantage
- Previous experience with storage systems, protocols, and NAND flash – strong advantage SKILLS:
- Capable of developing wide system view for complex embedded systems
- Excellent interpersonal skills
- Strong can-do attitude
Skills
Fpga Design,Verilog RTL based IP design,Testbench development
Click on Apply to know more.