UST
Website:
ust.com
Job details:
Role Description
Design DFT blocks depending on given specifications and guidelines Understand and follow the design life-cycle process, templates, guidelines, and checklists
- Understand DFT environment and design
- Participate in scan insertion and simulations phase
- Check test coverage and work on improving test coverage
- ATPG test pattern generation
- ICL/PDL generation
- Gate level DFT simulations
- Scan timing checks
- Spyglass checks
- 1-3 IP/Subsystems related blocks to be worked on
Skills
vlsi design,scan insertion,simulations,scan timing checks,
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