Interex semiconductor
Website:
interexsemi.com
Job details:
About the Role
Interex Semiconductor is seeking experienced ASIC Timing Engineers to join our growing team in Bengaluru.
We are looking for engineers with strong hands-on experience in Synthesis, Logic Equivalence Checking (LEC), and Static Timing Analysis (STA) who can independently drive timing closure and sign-off activities at block, sub-top, and top levels. The ideal candidate should possess strong timing fundamentals, excellent debugging skills, and experience working on complex ASIC/SoC designs.
Key Responsibilities
• Perform block-level synthesis and optimization using industry-standard EDA tools.
• Execute sub-top and top-level STA sign-off activities.
• Analyze timing reports and drive timing closure through timing ECO generation and implementation.
• Perform Logic Equivalence Checking (LEC) and support sign-off activities.
• Work closely with RTL and Physical Design teams to resolve timing and lint-related issues.
• Analyze setup/hold violations and drive closure across multiple clock domains.
• Support hierarchical timing analysis and sign-off methodologies.
• Develop and maintain TCL/Python scripts to improve timing analysis and flow automation.
Required Skills
• Minimum 5+ years of relevant experience in ASIC Timing Analysis and Synthesis.
• Strong expertise in Synthesis, LEC, and STA methodologies.
• Hands-on experience with Genus, Tempus, and Conformal.
• Experience with block-level synthesis and top-level timing sign-off.
• Strong understanding of multiple clock domain timing analysis.
• Solid knowledge of OCV, AOCV, SOCV, and clock tree concepts.
• Proficiency in TCL scripting. Python scripting experience is preferred.
• Strong debugging, analytical, and problem-solving skills.
Preferred Candidate Profile
• Proven experience driving timing closure and sign-off independently.
• Experience working on advanced ASIC/SoC projects.
• Strong communication and stakeholder management skills.
• Immediate joiners or candidates serving notice period are highly preferred.
• Candidates with less than 5 years of relevant STA/Synthesis experience are requested not to apply.
Apply
Interested candidates can apply through LinkedIn or share their updated resume to:
📧 nagu.m@interexsemi.com
If you know someone who would be a strong fit for this role, referrals are highly appreciated. Please feel free to share this opportunity within your professional network.
Click on Apply to know more.