ASIC RTL DesignL&T Technology Servicesfull-timeRequired skillscompilerAbout the role L&T Technology Services Website: ltts.com Job details: Below is the JD for RTL engg. We need to build strong RTL team. Minimum 5 years of work experience in ASIC RTL Design, Synthesis, STA & FVExperience in Logic design/micro-architecture/RTL coding is a must.Must have hands on experience with design and integration of complex multi clock domain blocksExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architectureHands on experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.Work closely with the Design verification and validation teams for pre/post Silicon debugHands on experience in Low power design is preferableExperience in Synthesis / Understanding of timing concepts for ASIC is must Click on Apply to know more. This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.