ASIC Desing Verification Lead - BangaloreUSTfull-timeRequired skillsGateAbout the role UST Website: ust.com Job details: Hi All,Experience8 to 15yearsJob DescriptionGood understanding of verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.Experience and knowledge in Verification of IP’s related to different applications. Good Knowledge in Power aware verification and Gate level verification is preferable. Should be able to understand the Full-chip Verification requirements as well and good knowledge in industry standard protocols. Verification for complex IP’s and close the Verification to the challenging milestones.Strong knowledge of AXI4/AXI5 protocolStrong understanding of Coherency rules in ACE and ACE5Experience with architecting BFMs/VIPsShould be able to handle a team of 3-4 engineers.IP Verification: VR creation as per the chip requirements and UVM/OVM Test benches creationSupport in building verification infrastructure at the chip level as per the requirements.Capable of handling multiple areas of IP Verification: RTL, Power Aware and Gate Level VerificationPlease forward your resume to jayalakshmi.r2@ust.comRegards,Jaya Click on Apply to know more. This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.