Graduate Engineer Trainee

As members of the implementation team, we will: Work together with the CPU design team to identify critical paths and timing bottlenecks across IP development, enabling accurate trade-off between the various performance metrics of the designs (frequency, IPC, power, area) Produce Power/Performance/area figures and help CPU micro-architecture improvement. Participate in existing CPU benchmarking to get the best possible Quality of Results. We are looking for individuals who have: Bachelors/ Master's degree or equivalent experience in Electronics & Communication Engineering / Electrical Engineering / Computer science from a reputed college / university, due to complete in 2025. Overall 70% in academics Exposure to synthesis/floor-planning/power planning, clock tree, place and route tools and techniques through school projects or internships Understanding of Power versus Performance versus Area tradeoff in typical CMOS design Exposure to CPU micro-architecture concepts (cache, MMU, pipeline…) Ability to schedule own workload and plan tasks Qualities that will help your application stand out: Hard-working, flexible, with strong communication Good interpersonal skills – oral and written. Willing to learn and explore new areas. Team-player. Motivated to continuously develop skills and accept a variety of responsibilities as part of supplying to the team's success.