FPGA Design Engineer
Arista Networks
- Salary
- $110k - $170k
- Experience
- 2+ yrs
- Location
- Roseville, California, United States
- Job type
- Full-time
Required skills
- Verilog
- SystemVerilog
- Python
- Tcl
- Shell
- PCIe
- Interlaken
- Ethernet
- SMBus
- SPI
- MDIO
- JTAG
- PTP
- sFlow
- PoE
- AXI
- AXI-Stream
- Logic Analyzer
- Oscilloscope
About the role
2+ years hands-on Verilog/SystemVerilog RTL design; proven control path design; experience with on-chip bus interfaces (I2C, SPI, MDIO, PCIe, AXI); preferred Ethernet data path, streaming bus, FPGA resource management, Python/Tcl scripting, lab debugging.
About Arista Networks
Provider of data-driven, client-to-cloud networking solutions.
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