Website:
bestnanotech.in
Job details:
Location: Pune / Bengaluru / Hyderabad, India |
Employment Type: Full-time
Role Summary
We are looking for an
AMS Verification Engineer with
2–3 years of relevant experience in
Analog Mixed-Signal verification at
IP and SoC level. The role involves behavioral modeling, mixed-signal testbench development, regression execution, testcase debug, and verification planning based on product specifications. The ideal candidate should have solid exposure to
Verilog / Verilog-AMS / wreal / SV-RNM, strong analog fundamentals, and hands-on experience with industry-standard AMS simulation tools.
Key Responsibilities
- Develop and maintain behavioral models using Verilog, Verilog-AMS, wreal, and SV-RNM.
- Perform AMS verification for IP-level and SoC-level designs.
- Create test plans from product specifications and verification requirements.
- Build and enhance mixed-signal testbenches for functional and corner-case verification.
- Execute regressions, analyze failures, and debug testcase and simulation issues.
- Improve verification coverage by adding corner scenarios and strengthening test content.
- Work closely with design, modeling, and verification teams to resolve mixed-signal issues.
- Use AMS simulation environments effectively across Cadence or Synopsys tool flows.
- Support automation tasks using scripting for regression handling and debug productivity.
- Contribute to verification documentation and delivery readiness in a schedule-driven environment.
Required Qualifications
- B.E./B.Tech with 3+ years of relevant experience, or M.Tech/MS with 2+ years of relevant experience in AMS Verification.
- Hands-on experience in AMS verification at IP or SoC level.
- Good understanding of behavioral modeling using Verilog / Verilog-AMS / wreal / SV-RNM.
- Strong exposure to mixed-signal testbench development and regression execution.
- Experience in test plan creation from product specifications.
- Strong debugging skills for simulation failures and functional/corner-case issues.
- Good understanding of analog fundamentals, including blocks such as PMIC, clock circuits, ADC, DAC.
- Working knowledge of Verilog is mandatory.
- Exposure to SystemVerilog / UVM is preferred.
- Experience with Python / Perl / Shell scripting for automation is preferred.
Preferred Tool Exposure
- Cadence: Xcelium, irun/xrun, Spectre
- Synopsys: XA-VCS
- Additional Plus: Eldo ADMS exposure
Domain Knowledge Preferred
- PMIC verification concepts
- Clock circuit behavior
- ADC / DAC verification basics
- Loop analysis exposure is an added advantage
Click on Apply to know more.