Physical Design Engineer

Invent the future with us. Recognized by Fast Company's 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team — we'd love to have you apply! About the role: As part of the Physical Design team at Ampere, you will be responsible for ASIC physical design and implementation on our cutting edge ARMv8 based server on chip solutions that will be the backbone of future data centers. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry. You will have an opportunity to work collaboratively with and learn from industry veteran designers and architects to create a breakthrough design for cloud computing. Our Physical Design Engineer will work with multi-functional global teams to implement Partition/Block level Constraint development, Synthesis, Floorplan, Place and Route, Timing closure, LEC, IR/EM and DRC/LVS closure for our next generation highly complex 5nm/7nm/advanced-node Server class Processor products. Being a Physical Design Engineer at Ampere® is interesting, challenging, and will expand your professional breadth. You will learn how a world-class design team develop their microprocessor using Ampere® Arm®-based platform plus our in-house and 3rd party IP portfolio. Also, you will understand pressure of being the leader team in the market, that push us to solve technical problems, and deliver product on time. The experience at Ampere® that you will possess will be valuable for your career path. What you'll achieve: Responsible for all aspect of physical design from RTL to GDS on sub-micron node, 16nm or lower Develop physical design methodologies, flow customization/automation, synthesis, LEC, floor-planning, power/clock distribution, IP block assembly, place & route, and timing closure. Implement top-level partitioning, chip integration, and assemble. Work with packaging, power-grid designer to plan on bumps, power-grid distribution for multiple domains at the chip-level. Implement chip-level routing, power-planning, and timing closure. Perform power and noise analysis, RC extraction, LEC and physical verification at the block and chip-level. About you: 5+ years of hand-on physical design experience from netlist to GDS on sub-micron node 28nm or lower Expertise in Cadence Innovus or Synopsys ICC2/Design Compiler Experience in block level place and route with multi voltage, multi corner designs In-depth understanding place and route flow Hand-on experience in layout verification, DRC fix, LVS with Calibre tool Experience with floor-plan trade off, placement and routing approaches, pre- and post-silicon ECO, timing closure, congestion resolution, IR-drop and crosstalk reduction techniques. Experience with high-speed Clock Tree Synthesis, topology and trade off Experience with signal integrity effect and solution Experience with constraint debug, timing closure are plus Experience with FinFET technology is a plus Good communication and teamwork skills Good English communications skills, both verbal and writing BS/MS/Ph.D in Electronic/Physic/Computer Engineering/Computer Science or a related field.

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.