- Location
- Santa Clara, California, United States
- Job type
- Full-time
Required skills
- Verilog
- SystemVerilog
- Python
- Perl
- Tcl
- UPF
About the role
Deep expertise in Memory PHY architecture, Verilog/SystemVerilog, scripting (Python/Perl/Tcl), mixed-signal integration, low-power design, and mentoring; bachelor's/master's/doctoral degree in EE/CE/CS preferred; not eligible for visa sponsorship.
About AMD
Leader in high-performance computing, graphics, and visualization technologies.
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