Senior Design Verification Engineer
Altera Digital Health
- Experience
- 9+ yrs
- Location
- Hyderabad, Telangana, India
- Job type
- Full-time
Required skills
- SystemVerilog
- UVM
- SystemVerilog Assertions (SVA)
- Verilog
- VHDL
- Python
- Perl
- Tcl
- AMBA (AXI, ACE, CHI, APB)
- PCIe
- Ethernet
About the role
Bachelor's or Master's in Electrical/Computer Engineering; 9+ years ASIC/FPGA verification experience; expertise in Verilog/VHDL, SystemVerilog, UVM; scripting in Python/Perl/Tcl; strong debugging and communication skills.
About Altera Digital Health
Independent designer and manufacturer of programmable logic devices.
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