FPGA IP Design and Verification Engineer
Altera Digital Health
- Experience
- 7+ yrs
- Location
- Hyderabad, Telangana, India
- Job type
- Full-time
Required skills
- VHDL
- Verilog
- SystemVerilog
- Tcl
- Perl
- Python
- Quartus
- Vivado
About the role
7+ years of semiconductor IP design verification experience; familiarity with HDL languages (VHDL, Verilog, SystemVerilog); scripting languages (Tcl, Perl, Python); FPGA tools (Quartus or Vivado) advantageous.
About Altera Digital Health
Independent designer and manufacturer of programmable logic devices.
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